An emitter-coupled logic circuit is generally composed of a differential amplifier stage and an emitter-follower stage which are connected in parallel between a high-level supply voltage source and a low-level supply voltage source and in series between signal input and output terminals of the emitter-coupled logic circuit. The differential amplifier stage in turn is made up essentially of a pair of n-p-n transistors connected in parallel between the high-level and low-level supply voltage sources. One of the two n-p-n transistors is to be turned on responsive to an input signal of high level and the other of the transistors is to be turned on responsive to an input signal of low level. On the other hand, the emitter-follower stage of the emitter-coupled logic circuit includes a series combination of an n-p-n transistor and a constant current source network connected between the high-level and low-level supply voltage sources. The n-p-n transistor thus forming part of the emitter-follower stage is activated either directly by a voltage supplied from the high-level supply voltage source or by a voltage supplied through the differential amplifier stage to produce an output signal of low or high level responsive to the input voltage of high or low level, respectively.
During transition of the output signal from the low level to high level, the n-p-n transistor of the emitter-follower stage receives charges at its emitter from a load capacitor connected in parallel with the n-p-n to form an emitter-follower network. For the transition of the output signal from the high level to low level, the load capacitor receives charges through the constant current source network until the capacitor is fully charged.
The constant current source network used in the emitter-follower stage is usually arranged such that the current to be supplied therefrom is far smaller than the emitter current of the associated transistor. For this reason, the high-to-low transition time of the output voltage of the emitter-coupled logic circuit is far longer than the low-to-high transition time of the output signal. Such a long high-to-low transition time of the output signal is apparently objectionable for speeding up the operation of the emitter-coupled logic circuit.